NCR Corporation has developed a scalable computer system architecture providing more effective scaling of multiprocessor performance than conventional system architectures. The scalable system architecture recognizes and overcomes many limitations of conventional system architectures, such as degradation caused by multiple processors sharing memory and memory busses, and overhead penalties associated with memory/cache coherency.
Key characteristics of this new architecture include: the use of multiple memory busses to reduce memory bus utilization and physical loading; the use of multi-ported memory to facilitate multiple busses and allow simultaneous use of different memory devices; the use of memory base coherency techniques that significantly reduce coherency overhead; and a symmetric view of system resources by all processors.
One implementation of this architecture employing dual system busses (12 and 14) and two dual-ported memory modules (16 and 18) connected between the system busses is shown in FIG. 1. Also shown in FIG. 1 are two Micro Channel.RTM. input/output (I/O) busses 32 and 42 and interface modules 28 and 30 connecting respective I/O busses 32 and 42 with the system busses. Thus, multiple bus masters, identified by reference numerals 34, 36, 38, 40, 44, 46 and 48 in FIG. 1, have access to memory modules 16 and 18. Arbitration systems may be employed to prioritize access to the system memory.
Each bus master which seeks read or write access with system memory may possess different memory transfer parameters for optimal operation. Memory caches and buffers can be employed to enhance memory transfer operations, but the wide variance in bandwidth requirements and performance characteristics among the bus masters makes it impossible to define a single buffer scheme that provides optimal performance for each bus master. For example, the Micro Channel bus architecture defines a high performance 80 Mbytes/second streaming transfer mode optimized for large block transfers. A bus master reading from memory using the streaming mode requires buffer logic which reads and buffers data from system memory relatively far ahead of the bus master. However, another bus master in the same system may only read a few bytes of information from the system memory every time it arbitrates for memory access. In this case, utilization of a buffering scheme which reads far ahead only to discard the bulk of prefetched data needlessly wastes system memory bandwidth.